The semiconductor LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Qoutputs. The common buffered Clock (CP) and Master Reset (MR)
input load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each Dinput, one setup time before the
LOW-to-HIGH clock transition,is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage
level on the MR input.
The device is useful for applications where the true output only
is required and the Clock and Master Reset are common to all storage elements. The inputs
tolerate up to 7V allowing interface of 5V systems to 3V systems.
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